Name
Title | ||
|---|---|---|
A scan shifting method based on clock gating of multiple groups for low power scan testing |
Abstract | ||
|---|---|---|
From the advent of very large scale integration (VLSI) design, a larger power consumption of a scan-based testing has been one of the most serious problems. The large number of scan cells lead to excessive switching activities during the scan shifting operations. In this paper, we present a new scan shifting method based on clock gating of multiple groups by reducing toggle rate of the internal combinational logic. This method prevents cumulative transitions caused by shifting operations of the scan cells. In addition, the existing compression schemes can be compatible with the proposed method without modification of decompression architecture. Experimental results on ITC'99 benchmark circuits and industrial circuits show that this shifting method reduces the scan shifting power in all cases. In spite of outperformed power, a burden of the extra logic is not necessary to be contemplated. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ISQED.2015.7085417 | ISQED |
Keywords | Field | DocType |
scan-based testing,design-for-testability (dft),low power scan testing,shifting power reduction,combinational circuits,logic gates,very large scale integration,switches,design for testability,clock gating,automatic test pattern generation | Boundary scan,Clock gating,Automatic test pattern generation,Logic gate,Computer science,Scan chain,Combinational logic,Electronic engineering,Real-time computing,Electronic circuit,Very-large-scale integration | Conference |
ISSN | Citations | PageRank |
1948-3287 | 6 | 0.47 |
References | Authors | |
15 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sungyoul Seo | 1 | 10 | 3.27 |
| Yong Lee 0002 | 2 | 6 | 0.47 |
| Joohwan Lee | 3 | 36 | 3.17 |
| Sungho Kang | 4 | 436 | 78.44 |