Name
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ASYNC.2014.15 | ASYNC |
Keywords | Field | DocType |
optimization,logic gates,protocols,static timing analysis,design automation | Logic synthesis,Logic gate,Logic optimization,Computer science,Design flow,Static timing analysis,Electronic design automation,Register-transfer level,Logic family,Embedded system | Conference |
Citations | PageRank | References |
8 | 0.54 | 16 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Matheus T. Moreira | 1 | 104 | 19.98 |
| Augusto Neutzling | 2 | 20 | 2.93 |
| Mayler G. A. Martins | 3 | 88 | 10.08 |
| André Inácio Reis | 4 | 134 | 21.33 |
| Renato P. Ribas | 5 | 204 | 33.52 |
| Ney Laert Vilar Calazans | 6 | 237 | 30.71 |