Name
Abstract | ||
|---|---|---|
Power/Ground (P/G) Through-Silicon-Vias (TSVs) in the Power Distribution Network (PDN) of Three-Dimensional-Integrated-Circuit (3D-IC) have a twofold impact on the delays of the surrounding gates. TSV fabrication causes thermal stress around TSVs, which results in significant carrier mobility variations in their vicinity. On the other hand, the insertion of P/G TSVs will change the voltage of each node in the power grid, which also impacts the delays of the connected gates. Thus, it is necessary to consider the combined effect on delay variation during the P/G TSV planning. In this work, we propose a methodology using Mixed-Integer-Bilinear-Programming (MIBLP) to optimize this delay variation by a refined P/G TSV allocation. Taking into account the impact of thermal stress as well as voltage drop on the circuit delay, we optimally plan the P/G TSVs to minimize the circuit delay for different keep-out zones (KOZs) and PDN pitches. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ASPDAC.2015.7058987 | ASP-DAC |
Keywords | Field | DocType |
pdn,power distribution network,miblp,integrated circuit interconnections,significant carrier mobility variations,voltage drop,thermal stresses,mixed-integer-bilinear-programming,three-dimensional integrated circuits,integer programming,circuit optimisation,connected gate delays,delay variation optimization,thermal stress,delays,circuit delay,pdn pitches,keep-out zones,stress-aware p/g tsv planning,power/ground through-silicon-vias,power grid,3d-ic,carrier mobility | Circuit delay,Computer science,Distribution networks,Voltage,Voltage drop,Stress (mechanics),Power grid,Electronic engineering,Electrical engineering,Electron mobility,Fabrication | Conference |
Citations | PageRank | References |
1 | 0.35 | 13 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shengcheng Wang | 1 | 13 | 4.29 |
| Farshad Firouzi | 2 | 275 | 20.28 |
| Fabian Oboril | 3 | 288 | 26.71 |
| Mehdi B. Tahoori | 4 | 1537 | 163.44 |