Name
Abstract | ||
|---|---|---|
Hybrid memory, where the DRAM acts as a buffer to the PRAM, is a promising configuration for main memory systems. It has the advantages of fast access time, high storage density and very low standby power. However, it also has reliability issues that need to be addressed. This paper focuses on low cost Error Control Coding (ECC)-based schemes for improving the reliability of hybrid memory. We propose three candidate systems that all guarantee block failure rate of 10-8 but differ in whether the DRAM and/or PRAM data get coded and the strength of the corresponding ECC code. The candidate systems are evaluated with respect to lifetime, Instruction Per Cycle (IPC) and energy. We show that (1) at lower Data Storage Time (DST), the proposed system which has different ECC schemes for DRAM and PRAM has the longest lifetime and one of the highest IPC; (2) at higher DST, stronger ECC codes are necessary for all the systems and longer lifetime can be achieved at the cost of decrease in IPC. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/SiPS.2014.6986076 | SiPS |
Keywords | DocType | Citations |
DST,ECC codes,IPC,phase change memories,Hybrid main memory,instruction per cycle,hybrid memory reliability,DRAM+PRAM,data storage time,error correction codes,DRAM chips,low cost ECC schemes,low cost error control coding schemes,reliability,DRAM-PRAM main memory systems | Conference | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Manqing Mao | 1 | 0 | 0.68 |
| Chengen Yang | 2 | 56 | 5.47 |
| ZiHan Xu | 3 | 21 | 2.16 |
| Yu Cao | 4 | 31 | 5.70 |
| Chaitali Chakrabarti | 5 | 1978 | 184.17 |