Name
Abstract | ||
|---|---|---|
A heuristic algorithm for assigning input variables to the decoders of a decoded-programmable logic array (PLA) is presented. In this algorithm, the number of inputs to each decoder is not restricted to two and the area overhead incurred by using multi-input decoders is considered in the cost function. Experimental results show that the areas of multi-input decoded-PLAs designed by this algorithm are smaller in many cases than those of decoded-PLAs with two-input decoders or standard PLAs.<> |
Year | DOI | Venue |
|---|---|---|
1988 | 10.1109/ICCAD.1988.122552 | ICCAD |
Keywords | Field | DocType |
decoded-programmable logic array,logic cad,multi-input decoders,logic arrays,heuristic algorithm,multi-input decoded-plas,vlsi,area overhead,cost function,programmable logic array | Logic synthesis,Complex programmable logic device,Sequential logic,Heuristic (computer science),Logic optimization,Computer science,Programmable logic array,Algorithm,Electronic engineering,Function block diagram,Programmable logic device | Conference |
Citations | PageRank | References |
3 | 0.46 | 5 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kuang-chien Chen | 1 | 347 | 30.84 |
| S. Muroga | 2 | 430 | 252.48 |