Name
Abstract | ||
|---|---|---|
This paper presents an efficient design-space exploration method to identify the Pareto solution for the relation between the execution time and the hardware area. Initially, our method takes a particular system mapping that is surely in the Pareto solution, and then repeats the local search and the update of the Pareto solution until the Pareto solution reaches a steady state. Compared to genetic-algorithm-based methods, we found that our method outputs the Pareto solution with a smaller number of explorations for larger design spaces. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/FCCM.2014.70 | FCCM |
Keywords | Field | DocType |
algorithm design and analysis,space exploration,field programmable gate arrays,transform coding,computer architecture,embedded systems | Algorithm design,Computer science,Load balancing (computing),Workload,Electronic system-level design and verification,Parallel computing,Traffic simulation,Real-time computing,Estimation theory,Design space exploration,Multi-core processor | Conference |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuki Ando | 1 | 9 | 3.65 |
| Seiya Shibata | 2 | 8 | 3.51 |
| Shinya Honda | 3 | 244 | 29.54 |
| Hiroyuki Tomiyama | 4 | 501 | 67.53 |
| Hiroaki Takada | 5 | 608 | 87.55 |