Name
Abstract | ||
|---|---|---|
Power consumption in current high-performance chip multiprocessors (CMPs) has become a major design concern. The current trend of increasing the core count aggravates this problem. On-chip caches consume a significant fraction of the total power budget. Most of the proposed techniques to reduce the energy consumption of these memory structures are at the cost of performance, which may become unacceptable for high-performance CMPs. On-chip caches in multi-core systems are usually deployed with a high associativity degree in order to enhance performance. Even first-level caches are currently implemented with eight ways. The concurrent access to all the ways in the cache set is costly in terms of energy. In this paper we propose an energy-efficient cache design, namely the Tag Filter Cache (TF-Cache) architecture, that filters some of the set ways during cache accesses, allowing to access only a subset of them without hurting the performance. Our cache for each way stores the lowest order tag bits in an auxiliary bit array and these bits are used to filter the ways that do not match those bits in the searched block tag. Experimental results show that, on average, the TF-Cache architecture reduces the dynamic power consumption up to 74.9% and 85.9% when applied to the L1 and L2 cache, respectively, for the studied applications. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/PDP.2015.58 | PDP |
Keywords | Field | DocType |
indexes | Tag RAM,Cache pollution,Computer science,Cache,Parallel computing,Page cache,Cache algorithms,Cache coloring,Bus sniffing,Computer hardware,Smart Cache | Conference |
ISSN | Citations | PageRank |
1066-6192 | 1 | 0.35 |
References | Authors | |
17 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Joan J. Valls | 1 | 9 | 1.83 |
| Julio Sahuquillo | 2 | 420 | 53.71 |
| Alberto Ros | 3 | 384 | 32.60 |
| María Engracia Gómez | 4 | 149 | 17.48 |