Name
Title | ||
|---|---|---|
13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS |
Abstract | ||
|---|---|---|
A 250K probing-resilient PUF array with measured 2GHz operation and total energy consumption of 13fJ/bit at 0.9V, 25°C is fabricated in 22nm tri-gate CMOS. Hybrid PUF circuit with integrated load modulation and run-time soft dark-bit mask generation enables identification of unstable PUF bits with 100% accuracy, eliminating the need for multiple voltage/temperature characterization while also reducing bit-error down to 1.94%. Transient behavior of the hybrid PUF cell, along with the use of balanced local clock routing improves resiliency to invasive power-up probing attacks by 75%. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ESSCIRC.2014.6942066 | european solid-state circuits conference |
Keywords | Field | DocType |
run-time soft dark-bit mask generation,CMOS integrated circuits,probing-resilient PUF array,balanced local clock routing,hybrid PUF circuit,size 22 nm,tri-gate CMOS,physically unclonable functions,temperature 25 degC,voltage 0.9 V,temperature 250 K,bit-error,frequency 2 GHz,integrated load modulation,multiple voltage-temperature characterization,invasive power-up probing attacks,transient behavior,energy consumption | Masking (art),Computer science,Voltage,Electronic engineering,CMOS,Modulation,Energy consumption,Clock routing | Conference |
ISSN | Citations | PageRank |
1930-8833 | 4 | 0.50 |
References | Authors | |
8 | 10 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sudhir Satpathy | 1 | 269 | 19.69 |
| S. Mathew | 2 | 462 | 76.59 |
| Jiangtao Li 0001 | 3 | 4 | 0.84 |
| Patrick Koeberl | 4 | 5 | 0.84 |
| Mark Anders | 5 | 315 | 50.81 |
| Himanshu Kaul | 6 | 456 | 51.07 |
| Gregory K. Chen | 7 | 298 | 32.96 |
| Amit Agarwal | 8 | 693 | 72.95 |
| S. K. Hsu | 9 | 521 | 52.06 |
| Ram Krishnamurthy | 10 | 650 | 74.63 |