Paper Info
Title
A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line
Abstract
A 12.5Gb/s forwarded clock receiver based on a DLL with a bang-bang PD is presented. The stuck locking is detected and averted by swapping edge and data samples at the output of the PD. Moreover, required delay range of the VCDL is reduced by half with the proposed sample swapping scheme. The prototype chip exhibits the power efficiency of 0.36pJ/bit and occupies 0.025mm2. Due to the wide jitter tracking bandwidth of DLL and the inherent jitter correlation between data and forwarded clock, the proposed receiver exhibits outstanding jitter tolerance whose corner frequency is higher than 300 MHz.
Year
DOI
Venue
2014
10.1109/ESSCIRC.2014.6942118
ESSCIRC
Keywords
Field
DocType
half-bit delay line,sample swapping,bang-bang pd,forwarded clock receiver,wide jitter tracking bandwidth,swapping edge,bit rate 12.5 gbit/s,jitter correlation,vcdl,data samples,stuck locking,forwarded-clock receiver,jitter tolerance,delay-locked loop,clocks,sample swapping scheme,receivers,dll,delay lines,delay lock loops,delay locked loop
Electrical efficiency,Swap (computer programming),Computer science,Delay-locked loop,Electronic engineering,Chip,Bandwidth (signal processing),Jitter,Cutoff frequency
Conference
ISSN
Citations 
PageRank 
1930-8833
2
0.43
References 
Authors
6
6
Name
Order
Citations
PageRank
Woo-Rham Bae14014.93
Gyu-Seob Jeong2219.00
Kwanseo Park3229.60
Sung-Yong Cho4214.41
Yoonsoo Kim512919.27
Deog-Kyoon Jeong6626119.05