Gyu-Seob Jeong - Citegraph

Author Info

Name	Affiliation	Papers
GYU-SEOB JEONG	Seoul Natl Univ, Dept Elect & Comp Engn, Seoul, South Korea	24
Collaborators	Citations	PageRank
40	21	9.00
Referers	Referees	References
72	285	77

Search Limit

100285

Publications (24 rows)

Collaborators (40 rows)

Referers (72 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Reference Spur Reduction Techniques for a Phase-Locked Loop.	1	0.37	2019
A Modulo-FIR Equalizer for Wireline Communications	0	0.34	2019
A 64gb/S 2.29pj/B Pam-4 Vcsel Transmitter With 3-Tap Asymmetric Ffe In 65nm Cmos	0	0.34	2019
4-Channel Push-Pull VCSEL Drivers for HDMI Active Optical Cable in 0.18-μm CMOS	0	0.34	2018
A 35-Gb/s 0.65-pJ/b Asymmetric Push-Pull Inverter-Based VCSEL Driver With Series Inductive Peaking in 65-nm CMOS.	1	0.36	2018
25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections.	0	0.34	2018
A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS	0	0.34	2018
A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS.	1	0.38	2018
A 0.015-mm2 Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology.	0	0.34	2017
Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection.	0	0.34	2017
A 0.015-mm $^{\text{2}}$ Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology	2	0.47	2017
A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and Gm-Regulated Resistive-Feedback Driver.	0	0.34	2017
Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology.	0	0.34	2016
A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS.	1	0.36	2016
20-Gb/s 5-VPP and 25-Gb/s 3.8-VPP Area-Efficient Modulator Drivers in 65-nm CMOS.	0	0.34	2016
A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology.	2	0.39	2016
20-Gb/s 5- $\text{V}_{\mathrm{PP}}$ and 25-Gb/s 3.8- $\text{V}_{\mathrm{PP}}$ Area-Efficient Modulator Drivers in 65-nm CMOS	0	0.34	2016
A 10 Gb/S Hybrid Pll-Based Forwarded Clock Receiver In 65-Nm Cmos	2	0.40	2015
A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm	1	0.36	2015
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process	5	0.69	2015
An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation	2	0.37	2015
A 20-Gb/s 1.27pJ/b low-power optical receiver front-end in 65nm CMOS	1	0.37	2014
A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process	0	0.34	2014
A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line	2	0.43	2014