Name
Abstract | ||
|---|---|---|
A 2-GS/s 6-bit flash analog-to-digital converter (ADC) in 90nm CMOS is presented. Using the reference-voltage-interpolated calibration reduces bandwidth requirements on the comparator to enable high sampling rates with low power consumption. The ADC consumes 28 mW and occupies 0.35 mm2. The proposed calibrated technique improves ENOB from 3.0 to 5.1 with an input sinusoid at Nyquist frequency. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ISCAS.2014.6865648 | ISCAS |
Keywords | Field | DocType |
power 28 mw,cmos integrated circuits,flash analog-to-digital converter,low power consumption,word length 6 bit,analogue-digital conversion,reference-voltage-interpolated calibration,low-power electronics,high-speed integrated circuits,low power,size 90 nm,high sampling rate,high-speed low-power calibrated flash adc,nyquist frequency,cmos,calibrated adc,transistors,low power electronics,calibration,capacitance,accuracy | Comparator,Computer science,Nyquist frequency,Effective number of bits,Flash ADC,Electronic engineering,CMOS,Bandwidth (signal processing),Integrated injection logic,Electrical engineering,Calibration | Conference |
ISSN | Citations | PageRank |
0271-4302 | 4 | 0.45 |
References | Authors | |
4 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hsuan-Yu Chang | 1 | 6 | 0.85 |
| Ching-Yuan Yang | 2 | 227 | 36.15 |