Name
Abstract | ||
|---|---|---|
The scalability of DRAM faces challenges from increasing power consumption and the difficulty of building high aspect ratio capacitors. Consequently, emerging memory technologies including Phase Change Memory (PCM), Spin-Transfer Torque RAM (STT-RAM), and Resistive RAM (ReRAM) are being actively pursued as replacements for DRAM memory. Among these candidates, ReRAM has superior characteristics such as high density, low write energy, and high endurance, making it a very attractive cost-efficient alternative to DRAM. In this paper, we present a comprehensive study of ReRAM-based memory systems. ReRAM's high density comes from its unique crossbar architecture where some peripheral circuits are laid below multiple layers of ReRAM cells. A crossbar architecture introduces special constraints on operating voltages, write latency, and array size. The access latency of a crossbar is a function of the data patterns involved in a write operation. These combined with ReRAM's exponential relationship between its write voltage and switching latency provide opportunities for architectural optimizations. This paper makes several key contributions. First, we study the crossbar architecture and describe trade-offs involving voltage drop, write latency, and data pattern. We then analyze microarchitectural enhancements such as double-sided ground biasing and multiphase reset operations to improve write performance. At the architecture level, a simple compression based data encoding scheme is proposed to further bring down the latency. As the compressibility of a block varies based on its content, write latency is not uniform across blocks. To mitigate the impact of slow writes on performance, we propose and evaluate a novel scheduling policy that makes writing decisions based on latency and activity of a bank. The experimental results show that our architecture improves the performance of a system using ReRAM-based main memory by about 44% over a conservative baseline and 14% over - n aggressive baseline on average, and has less than 10% performance degradation compared to an ideal DRAM-only system. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/HPCA.2015.7056056 | HPCA |
Keywords | Field | DocType |
stt-ram,phase change memory,spin-transfer torque ram,power consumption,double-sided ground biasing,microarchitectural enhancement,high aspect ratio capacitor,voltage drop,phase change memories,resistive ram,crossbar resistive memory architecture,pcm,write voltage,peripheral circuit,dram,switching latency,memory architecture,multiphase reset operation,compression based data encoding scheme,reram-based memory system | Dram,Phase-change memory,Capacitor,Latency (engineering),Computer science,Parallel computing,Voltage drop,Real-time computing,Crossbar switch,Scalability,Resistive random-access memory | Conference |
ISSN | Citations | PageRank |
1530-0897 | 83 | 2.68 |
References | Authors | |
37 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cong Xu | 1 | 1154 | 48.25 |
| Dimin Niu | 2 | 609 | 31.36 |
| Naveen Muralimanohar | 3 | 1295 | 57.58 |
| Rajeev Balasubramonian | 4 | 2302 | 116.79 |
| Tao Zhang | 5 | 402 | 19.22 |
| Shimeng Yu | 6 | 490 | 56.22 |
| Yuan Xie | 7 | 6430 | 407.00 |