Paper Info
Title
Self-adjusting mechanism to dynamically suppress the effect of PVT variations on clock skew
Abstract
Clock skew minimization is an important topic in the design of synchronous sequential circuit. As the process technology scaling, the effect of process/voltage/temperature (PVT) variations on clock skew has become a serious concern. It is known that, during the post-silicon stage, adjustable delay buffers (ADBs) can be utilized to eliminate the clock skew. However, unless ADBs have a self-adjusting mechanism, the clock skew caused by PVT variations cannot be completely suppressed. In this paper, we propose a self-adjusting mechanism that can dynamically configures the delays of ADBs to reduce the effect of PVT variations on clock skew. The proposed self-adjusting mechanism is composed of the following three stages: comparison, measurement, and quantification. Implementation results consistently show that the proposed self-adjusting mechanism can effectively suppress the clock skew caused by PVT variations.
Year
DOI
Venue
2014
10.1109/APCCAS.2014.7032781
APCCAS
Keywords
Field
DocType
sequential circuits,clock skew elimination,adb delay,adjustable delay buffer,clock skew minimization,self-adjusting mechanism,process-voltage-temperature variations,synchronous sequential circuit design,logic design,buffer circuits,pvt variation,process technology scaling,adjustable delay buffers,clock skew,clock distribution network,dynamical suppression,dynamic adjustment,pvt variations,post-silicon stage,registers,synchronization
Timing failure,Clock gating,Computer science,Control theory,Clock domain crossing,Electronic engineering,Clock skew,Synchronous circuit,Digital clock manager,Clock angle problem,CPU multiplier
Conference
Citations 
PageRank 
References 
0
0.34
10
Authors
3
Name
Order
Citations
PageRank
Tsung-Tang Lin100.34
Wen-Pin Tu2214.32
Shih-Hsu Huang320338.89