Paper Info
Title
A power efficient reconfigurable system-in-stack: 3D integration of accelerators, FPGAs, and DRAM
Abstract
Increasing computing power efficiency has become more important as more applications are moving to mobile platforms, which tend to have a limited power available. Being able to perform a wide variety of computations efficiently is especially important for power constrained embedded applications such as unmanned aerial vehicles (UAVs), which may not be able to send the data out for processing and must perform some of the processing on-board. This paper describes a 3D FPGA-DRAM architecture that can not only deliver the necessary flexibility, by using FPGAs, but also provide the computing efficiency in the form of floating-point arithmetic accelerators that is required for UAVs. We examine the efficiency of this system in 65 nm, 90 nm, and 130 nm CMOS technologies and report simulation results showing a peak computing efficiency of 28.94 GFLOPs/W for a 4,096 point 1 dimensional FFT and 25.03 GFLOPs/W for a 1,024 point × 1,024 point 2 dimensional FFT.
Year
DOI
Venue
2014
10.1109/SOCC.2014.6948892
System-on-Chip Conference
Keywords
Field
DocType
CMOS integrated circuits,DRAM chips,field programmable gate arrays,logic design,three-dimensional integrated circuits,3D FPGA-DRAM architecture,CMOS technologies,FFT,UAV,computing power efficiency,floating-point arithmetic accelerators,power efficient reconfigurable system-in-stack,size 130 nm,size 65 nm,size 90 nm,unmanned aerial vehicles
Electrical efficiency,Dram,Power efficient,FLOPS,Computer science,Field-programmable gate array,CMOS,Fast Fourier transform,Embedded system,Computation
Conference
Citations 
PageRank 
References 
1
0.36
0
Authors
5
Name
Order
Citations
PageRank
Peter Gadfort110.36
Aravind Dasu2104.47
Ali Akoglu315729.40
Yoon Kah Leow410.36
Michael Fritze510.36