Name
Title | ||
|---|---|---|
A 6.25Gb/s feed-forward equaliser in 0.18μm CMOS using delay locked loop with load calibration |
Abstract | ||
|---|---|---|
A 6.25Gb/s 3-tap T/2-spaced feed-forward equaliser (FFE) is realized in 0.18μm CMOS Technology. The proposed FFE can be used to reduce the inter-symbol interference (ISI). A high frequency boost delay element using source capacitive degeneration is adopted to meet the high speed requirement. Additionally, a delay locked loop and a load calibration technique are used to overcome process variations. The chip including I/O pads occupies an area of 0.76×0.67mm2 and consumes a power of 108mW with 1.8V power supply. Post simulation results show that the proposed FFE works properly at 6.25Gb/s and more than 70% eye opening can be obtained. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/CSNDSP.2014.6923825 | CSNDSP |
Keywords | Field | DocType |
delay locked loop,feed-forward equaliser,cmos integrated circuits,calibration,feedforward,load calibration technique,0.18um cmos,high frequency boost delay element,source capacitive degeneration,low-power electronics,6.25gb/s,power 108 mw,voltage 1.8 v,cmos technology,size 0.18 mum,load calibration,3-tap t/2-spaced feed-forward equaliser,equalisers,delay lock loops,intersymbol interference,bandwidth,logic gates,low power electronics | Logic gate,Computer science,Delay-locked loop,Bridged T delay equaliser,Chip,Real-time computing,Capacitive sensing,CMOS,Equaliser,Feed forward | Conference |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yongsheng He | 1 | 0 | 0.34 |
| Qingsheng Hu | 2 | 10 | 5.52 |
| Jun Feng | 3 | 0 | 0.68 |