Name
Abstract | ||
|---|---|---|
A GPU-based timing-aware ATPG is proposed to generate a compact high-quality test set. The test generation algorithm backtraces and propagates along multiple long paths so that many test patterns are generated at the same time. Generated test patterns are then fault simulated and selected. Compared with an 8-core CPU-based timing-aware commercial ATPG, the proposed GPU-based technique achieved 36% test length reductions on large benchmark circuits while the SDQL quality remains almost the same. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ETS.2014.6847835 | ETS |
Keywords | Field | DocType |
test length reductions,compact high-quality test set generation,integrated circuit testing,benchmark circuits,gpu,graphics processing units,gpu-based timing-aware test generation technique,automatic test pattern generation,sdql quality,delays,small delay defect,test pattern generation,gpu-based timing-aware atpg,small delay defects,test generation,parallel,kernel | Automatic test pattern generation,Fault coverage,Computer science,Parallel computing,Real-time computing,Test compression,Electronic circuit,Test set | Conference |
ISSN | Citations | PageRank |
1530-1877 | 1 | 0.37 |
References | Authors | |
5 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kuan-Yu Liao | 1 | 1 | 0.37 |
| Po-Juei Chen | 2 | 1 | 0.37 |
| Ang-Feng Lin | 3 | 1 | 0.37 |
| James Chien-Mo Li | 4 | 187 | 27.16 |
| Michael S. Hsiao | 5 | 1 | 0.37 |
| Laung-terng Wang | 6 | 601 | 44.22 |