Paper Info
Title
Efficient and secure intellectual property (IP) design with split fabrication
Abstract
Split fabrication, the process of splitting an IC into an untrusted and trusted tier, facilitates access to the most advanced semiconductor manufacturing capabilities available in the world without requiring disclosure of design intent. While researchers have investigated the security of logic blocks in the context of split fabrication, the security of IP blocks, another key component of an SoC, has not been examined. Our security analysis of IP block designs, specifically embedded memory and analog components, shows that they are vulnerable to “recognition attacks” at the untrusted foundry due to the use of standardized floorplans and leaf cell layouts. We propose methodologies to design these blocks efficiently and securely, and demonstrate their effectiveness using 130nm split fabricated testchips.
Year
DOI
Venue
2014
10.1109/HST.2014.6855561
Hardware-Oriented Security and Trust
Keywords
Field
DocType
industrial property,integrated circuit design,security,system-on-chip,IC splitting,IP block security,IP design security,SoC,analog components,embedded memory,intellectual property design security,leaf cell layouts,logic block security,recognition attacks,semiconductor manufacturing capabilities,size 130 nm,split fabricated testchips,split fabrication,standardized floorplans,trusted tier,untrusted foundry,untrusted tier,Circuit obfuscation,Design for trust,Hard IP,Hardware security,IP security,Split fabrication.
IPsec,Hardware security module,Computer science,Semiconductor device fabrication,Decision support system,Real-time computing,Security analysis,Intellectual property,Design intent,Fabrication,Embedded system
Conference
Citations 
PageRank 
References 
24
1.30
8
Authors
6
Name
Order
Citations
PageRank
Kaushik Vaidyanathan1664.09
Renzhi Liu2312.73
H. Ekin Sumbul3512.57
Qiuling Zhu4675.31
Franz Franchetti597488.39
Larry Pileggi61029108.97