| A High Throughput Hardware Accelerator for FFTW Codelets: A First Look | 0 | 0.34 | 2022 |
| A Compiler for Sound Floating-Point Computations using Affine Arithmetic | 0 | 0.34 | 2022 |
| An Interval Compiler for Sound Floating-Point Computations | 0 | 0.34 | 2021 |
| Leveraging High Dimensional Spatial Graph Embedding as a Heuristic for Graph Algorithms | 0 | 0.34 | 2021 |
| Graph Embedding and Field Based Detection of Non-Local Webs in Large Scale Free Networks | 0 | 0.34 | 2021 |
| Optimized Quantum Circuit Generation with SPIRAL | 0 | 0.34 | 2021 |
| An Auto-Tuning With Adaptation Of A64 Scalable Vector Extension For Spiral | 0 | 0.34 | 2021 |
| Massive Scaling of MASSIF: Algorithm Development and Analysis for Simulation on GPUs | 0 | 0.34 | 2020 |
| Verified Translation Between Purely Functional and Imperative Domain Specific Languages in HELIX. | 0 | 0.34 | 2020 |
| A Flexible Framework For Multidimensional Dfts | 0 | 0.34 | 2020 |
| GBTLX: A First Look | 0 | 0.34 | 2020 |
| FFTE on SVE: SPIRAL-Generated Kernels | 2 | 0.41 | 2020 |
| Fesia: A Fast And Simd-Efficient Set Intersection Approach On Modern Cpus | 0 | 0.34 | 2020 |
| A Flexible Framework for Parallel Multi-Dimensional DFTs. | 0 | 0.34 | 2019 |
| FFTX for Micromechanical Stress-Strain Analysis | 0 | 0.34 | 2019 |
| Efficient SpMV Operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization | 5 | 0.43 | 2019 |
| Fast and accurate object detection in high resolution 4K and 8K video using GPUs | 1 | 0.42 | 2018 |
| High Performance Zero-Memory Overhead Direct Convolutions. | 0 | 0.34 | 2018 |
| Large-Scale Algorithm Design for Parallel FFT-based Simulations on GPUs | 1 | 0.41 | 2018 |
| HELIX - a case study of a formal verification of high performance program generation. | 0 | 0.34 | 2018 |
| SPIRAL: Extreme Performance Portability. | 7 | 0.55 | 2018 |
| PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV | 2 | 0.36 | 2018 |
| Linear Algebraic Formulation of Edge-centric K-truss Algorithms with Adjacency Matrices | 3 | 0.44 | 2018 |
| FFTX and SpectralPack: A First Look | 4 | 0.53 | 2018 |
| High Assurance Code Generation for Cyber-Physical Systems | 1 | 0.38 | 2017 |
| Mixed data layout kernels for vectorized complex arithmetic | 2 | 0.41 | 2017 |
| Algorithm and hardware co-optimized solution for large SpMV problems | 2 | 0.40 | 2017 |
| Algebraic description and automatic generation of multigrid methods in SPIRAL. | 0 | 0.34 | 2017 |
| First look: Linear algebra-based triangle counting without matrix multiplication | 7 | 0.47 | 2017 |
| A scale-free structure for real world networks | 0 | 0.34 | 2017 |
| Big Data Computation Of Taxi Movement In New York City | 5 | 0.46 | 2016 |
| Accelerating Architectural Simulation Via Statistical Techniques: A Survey. | 9 | 0.50 | 2016 |
| Automating the Last-Mile for High Performance Dense Linear Algebra. | 0 | 0.34 | 2016 |
| Compilers, hands-off my hands-on optimizations. | 2 | 0.38 | 2016 |
| HAMLeT Architecture for Parallel Data Reorganization in Memory | 3 | 0.38 | 2016 |
| Mathematical foundations of the GraphBLAS | 29 | 1.45 | 2016 |
| FFTs with Near-Optimal Memory Access Through Block Data Layouts: Algorithm, Architecture and Design Automation | 3 | 0.48 | 2016 |
| Enabling portable energy efficiency with memory accelerated library | 1 | 0.36 | 2015 |
| Generating Optimized Fourier Interpolation Routines for Density Functional Theory Using SPIRAL | 0 | 0.34 | 2015 |
| Optimizing Space Time Adaptive Processing through accelerating memory-bounded operations | 0 | 0.34 | 2015 |
| Energy-Efficient Abundant-Data Computing: The N3XT 1,000x | 24 | 1.82 | 2015 |
| A synthesis methodology for application-specific logic-in-memory designs | 1 | 0.37 | 2015 |
| Data reorganization in memory using 3D-stacked DRAM | 49 | 1.15 | 2015 |
| An ensemble technique for estimating vehicle speed and gear position from acoustic data | 0 | 0.34 | 2015 |
| Barometric and GPS altitude sensor fusion | 2 | 0.42 | 2014 |
| Understanding the design space of DRAM-optimized hardware FFT accelerators | 12 | 0.65 | 2014 |
| Efficient and secure intellectual property (IP) design with split fabrication | 24 | 1.30 | 2014 |
| Algorithm/hardware co-optimized SAR image reconstruction with 3D-stacked logic in memory | 3 | 0.39 | 2014 |
| Special issue on automatic application tuning for HPC architectures | 0 | 0.34 | 2014 |
| A stencil compiler for short-vector SIMD architectures | 57 | 2.03 | 2013 |
