Name
Abstract | ||
|---|---|---|
This paper proposes a new parallel test access strategy for multiple identical cores in a network-on-chip (NoC). The proposed test strategy takes advantage of the regular design of NoC to reduce both test area overhead and test time. The proposed NoC reused test access mechanism (TAM) adopted a pipelining structure and a deterministic test data routing algorithm in order to reuse the full bandwidth of links in the NoC. Also, the architecture has complete scalability according to the number of cores and applications for 3D environment are also represented. Experimental results show that the proposed TAM can test multiple cores with the same test time as a single core and negligible hardware overhead. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ATS.2014.26 | ATS |
Keywords | Field | DocType |
integrated circuit testing,network routing,microprocessor chips,noc,parallel test, multiple identical cores, noc, tam,test access mechanism,parallel test access strategy,tam,multiprocessing systems,test data routing algorithm,multiple identical cores,test area overhead,parallel test,noc-based multicore system,network-on-chip,routing,multicore processing,testing,hardware,system on chip | Pipeline (computing),Single-core,System on a chip,Computer science,Reuse,Parallel computing,Real-time computing,Bandwidth (signal processing),Multi-core processor,Test strategy,Scalability,Embedded system | Conference |
ISSN | Citations | PageRank |
1081-7735 | 8 | 0.46 |
References | Authors | |
15 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Taewoo Han | 1 | 79 | 8.41 |
| Inhyuk Choi | 2 | 15 | 4.75 |
| Hyunggoy Oh | 3 | 14 | 4.80 |
| Sungho Kang | 4 | 12 | 6.64 |