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HYUNGGOY OH
Author Info
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Name
Affiliation
Papers
HYUNGGOY OH
Yonsei Univ, Comp Syst & Reliable SoC Lab, Dept Elect & Elect Engn, Seoul, South Korea
13
Collaborators
Citations
PageRank
9
14
4.80
Referers
Referees
References
43
223
91
Search Limit
100
223
Publications (13 rows)
Collaborators (9 rows)
Referers (43 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Low Power Scan Chain Architecture Based on Circuit Topology
0
0.34
2018
Test Resource Reused Debug Scheme to Reduce the Post-Silicon Debug Cost.
0
0.34
2018
Thermal Aware Test Scheduling for NTV Circuit.
2
0.49
2018
Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test
0
0.34
2018
Reconfigurable Scan Architecture For Test Power And Data Volume Reduction
0
0.34
2017
A Novel X-Filling Method For Capture Power Reduction
0
0.34
2017
A selective error data capture method using on-chip DRAM for silicon debug of multi-core design
0
0.34
2017
DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores.
0
0.34
2017
Proof of Concept of Home IoT Connected Vehicles.
3
0.46
2017
An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time.
1
0.35
2017
Process Variation-Aware Bridge Fault Analysis
0
0.34
2016
Parallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores.
0
0.34
2016
A Scalable and Parallel Test Access Strategy for NoC-Based Multicore System
8
0.46
2014
1