Name
Abstract | ||
|---|---|---|
Excessive test power dissipation results in over-testing, IR-drop, yield loss and even heat damage to the circuit under test (CUT). An efficient scan-shift power reduction scheme based on scan chain partitioning and test vector reordering is presented in this paper. After partitioning the scan chains into several segments equally, a heuristic ant colony optimization (ACO) algorithm is introduced to reorder the test vectors to minimize the clashes between the previous test response and current test vector, which leads to scan-shift power reduction further. Experimental results show that the proposal can achieve 3.48% scan-shift power reduction on average with the help of ACO test vectors reordering after scan partitioning. Furthermore, the proposed scan-shift power reduction technique can be acceptable for any scan-based testing architecture without affecting test application time, test fault coverage, performance and/or routing cost of the CUT. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ICECS.2014.7050031 | ICECS |
Keywords | Field | DocType |
integrated circuit testing,power aware computing,scan chain partitioning,ant colony optimisation,circuit optimisation,scan-based testing architecture,test power dissipation,heuristic aco algorithm,cut,performance evaluation,scan-shift power reduction scheme,test vector reordering,heuristic ant colony optimization algorithm,circuit under test | Ant colony optimization algorithms,Automatic test pattern generation,Test vector,Heuristic,Fault coverage,Computer science,Dissipation,Parallel computing,Scan chain,Test compression | Conference |
Citations | PageRank | References |
1 | 0.35 | 10 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tiebin Wu | 1 | 1 | 0.35 |
| Li Zhou | 2 | 69 | 2.77 |
| Hengzhu Liu | 3 | 86 | 23.28 |