Name
Abstract | ||
|---|---|---|
Counters are among the basic blocks in every digital system. We propose a novel high-speed counter with a constant counting rate, independent of its length. Exploiting special features of the binary arithmetic system and adopting prescaling techniques, a segmented counter architecture is introduced. Particularly, to realize a counter of any length properly, two designed modules of four-bit counter are used in a systolic manner. The counting rate is bounded by the delay of two basic gates of three inputs plus the delay of a T F/F. In AMS 0.6 mum technology a maximum of 430 MHz counting frequency is achieved. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/ICECS.2003.1301719 | ICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 |
Keywords | DocType | Citations |
vlsi,hardware description languages,logic gates | Conference | 2 |
PageRank | References | Authors |
0.42 | 1 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Athanasios P. Kakarountas | 1 | 80 | 8.21 |
| george theodoridis | 2 | 67 | 14.19 |
| Kyriakos S. Papadomanolakis | 3 | 2 | 0.42 |
| Costas E Goutis | 4 | 186 | 25.76 |