| Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions' architectures. | 2 | 0.37 | 2016 |
| Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs. | 3 | 0.41 | 2016 |
| Array Size Computation under Uniform Overlapping and Irregular Accesses. | 0 | 0.34 | 2016 |
| A Methodology for Speeding up MVM for Regular, Toeplitz and Bisymmetric Toeplitz Matrices | 2 | 0.35 | 2014 |
| On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs. | 2 | 0.37 | 2014 |
| A Matrix–Matrix Multiplication methodology for single/multi-core architectures using SIMD | 7 | 0.46 | 2014 |
| A Systematic Flow for Developing Totally Self-Checking Architectures for SHA-1 and SHA-2 Cryptographic Hash Families. | 1 | 0.35 | 2013 |
| High-performance FPGA implementations of the cryptographic hash function JH. | 1 | 0.36 | 2013 |
| A data locality methodology for matrix–matrix multiplication algorithm | 6 | 0.45 | 2012 |
| On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function. | 1 | 0.39 | 2012 |
| High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach. | 0 | 0.34 | 2012 |
| Cipher Block Based Authentication Module: a Hardware Design Perspective | 2 | 0.40 | 2011 |
| A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization | 8 | 0.54 | 2011 |
| Decoupled Processors Architecture for Accelerating Data Intensive Applications using Scratch-Pad Memory Hierarchy | 0 | 0.34 | 2010 |
| Ultra High Speed SHA-256 Hashing Cryptographic Module for IPSec Hardware/Software Codesign. | 2 | 0.42 | 2010 |
| Designs and comparisons of authentication modules for IPSec in configurable and extensible embedded processor. | 0 | 0.34 | 2010 |
| A Top-Down Design Methodology for Ultrahigh-Performance Hashing Cores | 13 | 0.82 | 2009 |
| Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays | 1 | 0.35 | 2009 |
| Resource aware mapping on coarse grained reconfigurable arrays | 16 | 0.70 | 2009 |
| Efficient high-performance implementation of JPEG-LS encoder. | 20 | 1.46 | 2008 |
| Performance and energy consumption improvements in microprocessor systems utilizing a coprocessor data-path | 2 | 0.40 | 2008 |
| Speedups from extending embedded processors with a high-performance coarse-grained reconfigurable data-path | 0 | 0.34 | 2008 |
| Speedups and Energy Savings of Microprocessor Platforms with a Coarse-Grained Reconfigurable Data-Path | 0 | 0.34 | 2007 |
| Implementation of HSSec: a high-speed cryptographic co-processor. | 1 | 0.40 | 2007 |
| Exploring the speedups of embedded microprocessor systems utilizing a high-performance coprocessor data-path | 0 | 0.34 | 2007 |
| Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture | 5 | 0.45 | 2007 |
| A unified evaluation framework for coarse grained reconfigurable array architectures | 5 | 0.44 | 2007 |
| Compiler assisted architectural exploration for coarse grained reconfigurable arrays | 1 | 0.36 | 2007 |
| Server side hashing core exceeding 3 Gbps of throughput | 6 | 0.43 | 2007 |
| Improving performance and energy consumption in embedded microprocessor platforms with a flexible custom coprocessor data-path | 0 | 0.34 | 2007 |
| Speedups in embedded systems with a high-performance coprocessor datapath | 1 | 0.37 | 2007 |
| Performance optimization of embedded applications in a hybrid reconfigurable platform | 0 | 0.34 | 2007 |
| Temporal and System Level Modifications for High Speed VLSI Implementations of Cryptographic Core | 0 | 0.34 | 2006 |
| Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic | 0 | 0.34 | 2006 |
| High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications | 12 | 1.32 | 2006 |
| Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware | 2 | 0.38 | 2006 |
| Partitioning Methodology for Heterogeneous Reconfigurable Functional Units | 6 | 0.47 | 2006 |
| A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems | 1 | 0.53 | 2006 |
| Performance improvements from partitioning applications to FPGA hardware in embedded SoCs | 2 | 0.40 | 2006 |
| Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures | 10 | 0.72 | 2006 |
| Partitioning DSP applications to different granularity reconfigurable hardware. | 0 | 0.34 | 2005 |
| A method for partitioning applications in hybrid reconfigurable architectures | 2 | 0.40 | 2005 |
| Optimizing SHA-1 hash function for high throughput with a partial unrolling study | 6 | 0.91 | 2005 |
| Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays | 11 | 0.76 | 2005 |
| Performance gains from partitioning embedded applications in Processor-FPGA socs | 0 | 0.34 | 2005 |
| Performance Improvements using Coarse-Grain Reconfigurable Logic in Embedded SoCs | 2 | 0.39 | 2005 |
| A high performance data-path to accelerate DSP kernels. | 0 | 0.34 | 2004 |
| Efficient implementation of the keyed-hash message authentication code (HMAC) using the SHA-1 hash function. | 10 | 0.73 | 2004 |
| Power efficient data path synthesis of sum-of-products computations | 2 | 0.46 | 2003 |
| A novel high-speed counter with counting rate independent of the counter's length. | 2 | 0.42 | 2003 |
