Name
Abstract | ||
|---|---|---|
Regular fabrics are expected to mitigate manufacturing process variations, increasing the fabrication yield in deep sub-micron CMOS technologies. This paper presents an extensive analysis of lithography behaviour of transistor-array based regular fabrics. Four different approaches presented in the literature (VCC, INVA, VCLB and VCTA) have been evaluated through lithography simulations. The well-established concept of edge placement error (EPE) has been taken into account as lithography behavior metric. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/NORCHP.2012.6403145 | 2009 NORCHIP |
Keywords | Field | DocType |
cmos integrated circuits,lithography,transistors | Transistor array,Computer science,Electronic engineering,CMOS,Lithography,Computational lithography,Transistor,Next-generation lithography,Electrical engineering,Fabrication,Manufacturing process | Conference |
Citations | PageRank | References |
1 | 0.35 | 14 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vinícius Dal Bem | 1 | 19 | 4.07 |
| André Inácio Reis | 2 | 134 | 21.33 |
| Renato P. Ribas | 3 | 204 | 33.52 |