Name
Title | ||
|---|---|---|
A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability |
Abstract | ||
|---|---|---|
A ferroelectric-based (FE-based) non-volatile flip-flop (NWF) is proposed for low-power LSI. Since leakage current in a logic circuit can be cut off by non-volatile storage capability of NVFFs, the standby power is reduced to zero. The use of complementarily stored data in coupled FE capacitors makes it possible to achieve 88% reduction of FE capacitor size while maintaining a wide read voltage margin of 240mV (minimum) at 1.5V, which results in 2.4pJ low access energy with 10-year, 85°C data retention capability. An access speed of FE capacitors can be adaptively changed according to required retention time, which becomes 1.6/fS for 10-year data retention, and 170ns for 10-hour data retention. Especially, short-term data retention is suitable for power gating implementation. Applying the proposed circuitry in 32bit CPU of a vital sensor LSI, its power consumption becomes 13% of that of conventional one with area overhead of 64% using 130nm CMOS with Pb(Zr, Ti)O3(PZT) thin films. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ASSCC.2014.7008850 | A-SSCC |
Keywords | Field | DocType |
cmos digital integrated circuits,ferroelectric devices,flip-flops,large scale integration,logic circuits,low-power electronics,random-access storage,cmos,fe capacitors,nwf,pzt,capacitor size reduction,energy 2.4 pj,ferroelectric-based nonvolatile flip-flop,leakage current,logic circuit,low-power lsl,nonvolatile storage capability,power consumption,power gating implementation,short-term data retention,size 130 nm,temperature 85 degc,thin films,time 1.6 mus,time 10 hour,time 10 year,time 170 ns,vital sensor,voltage 1.5 v,voltage 240 mv,word length 32 bit,ferroelectric capacitor,low power,microporcessor,non-volatile flip-flop,non-volatile logic,capacitors,cmos integrated circuits,iron | Capacitor,Data retention,Leakage (electronics),Standby power,Computer science,CMOS,Electronic engineering,Power gating,Electrical engineering,Integrated injection logic,Ferroelectric capacitor | Conference |
Citations | PageRank | References |
7 | 0.55 | 4 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| hiromitsu kimura | 1 | 7 | 0.55 |
| takaaki fuchikami | 2 | 7 | 0.55 |
| kyoji maramoto | 3 | 7 | 0.55 |
| yoshikazu fujimori | 4 | 7 | 0.55 |
| Shintaro Izumi | 5 | 82 | 31.56 |
| Hiroshi Kawaguchi | 6 | 37 | 21.08 |
| masahiko yoshimoto | 7 | 117 | 34.06 |