Name
Abstract | ||
|---|---|---|
A wide bandwidth, high sample rate 3rd order continuous-time ΔΣ modulator using VCO-based integrators is presented. Non-idealities caused by VCOs at the modulator frontend are addressed using both circuit- and architecture-level techniques. Fabricated in 65 nm CMOS, the prototype modulator operates at 1.28 GS/s and achieves a dynamic range of 75 dB, SNR of 71 dB in 50 MHz bandwidth, while consuming 38 mW of total power. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/VLSIC.2014.6858395 | VLSIC |
Keywords | Field | DocType |
cmos integrated circuits,delta-sigma modulation,voltage-controlled oscillators,3rd order ct-δς modulator,cmos process,vco-based integrators,architecture-level techniques,circuit-level techniques,frequency 50 mhz,modulator frontend,power 38 mw,size 65 nm | Dynamic range,Computer science,Sampling (signal processing),Integrator,Voltage-controlled oscillator,Electronic engineering,CMOS,Modulation,Bandwidth (signal processing),Electrical engineering | Conference |
Citations | PageRank | References |
0 | 0.34 | 2 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Brian Young | 1 | 0 | 0.34 |
| Karthikeyan Reddy | 2 | 74 | 10.57 |
| Sachin Rao | 3 | 15 | 3.55 |
| Amr Elshazly | 4 | 242 | 28.08 |
| Tejasvi Anand | 5 | 110 | 16.98 |
| Pavan Kumar Hanumolu | 6 | 554 | 84.82 |