Paper Info
Title
16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS
Abstract
Energy-efficient networks-on-chip (NoCs) are key enablers for exa-scale computation by shifting power budget from communication toward computation. As core counts scale into the 100s, on-chip interconnect fabrics must support increasing heterogeneity and voltage/clock domains. Synchronous NoCs require either a single clock distributed globally or clock-crossing data FIFOs between clock domains [1]. A global clock requires costly full-chip margining and significant power and area for clock distribution, while synchronizing data FIFOs add power, performance, and area overhead per clock crossing. Source-synchronous NoCs mitigate these penalties by forwarding a local clock along with each packet, but still suffer from high data storage power due to packet switching. Circuit switching removes intra-route data storage, but suffers from low network utilization due to serialized channel setup and data transfer [2]. Hybrid packet/circuit switching parallelizes these operations for higher network utilization. A 16×16 mesh, 112b data, 256 voltage/clock domain NoC with source-synchronous operation, hybrid packet/circuit-switched flow control, and ultra-low-voltage optimizations is fabricated in 22nm tri-gate CMOS [3] to enable: i) 20.2Tb/s total throughput at 0.9V, 25°C, ii) a 2.7× increase in bisection bandwidth to 2.8Tb/s and 93% reduction in circuit-switched latency at 407ps/hop through source-synchronous operation, iii) a 62% latency improvement and 55% increase in energy efficiency to 7.0Tb/s/W through circuit switching, iv) a peak energy efficiency of 18.3Tb/s/W for near-threshold operation at 430mV, 25°C, and v) ultra-low-voltage operation down to 340mV with router power scaling to 363μW.
Year
DOI
Venue
2014
10.1109/ISSCC.2014.6757432
Solid-State Circuits Conference Digest of Technical Papers
Keywords
DocType
ISSN
cmos integrated circuits,circuit switching,integrated circuit design,low-power electronics,network-on-chip,packet switching,synchronisation,bit rate 20.2 tbit/s,clock-crossing data fifo,energy-efficient networks-on-chip,exascale computation,global clock,hybrid packet-circuit-switched flow control,intraroute data storage,on-chip interconnect fabrics,power 363 muw,size 22 nm,source-synchronous noc,source-synchronous operation,temperature 25 c,trigate cmos,ultralow-voltage optimizations,voltage 0.9 v,voltage 340 mv,voltage 430 mv,voltage-clock domains,low power electronics,network on chip
Conference
0193-6530
Citations 
PageRank 
References 
21
0.96
8
Authors
10
Name
Order
Citations
PageRank
Gregory K. Chen129832.96
Mark A. Anders218517.43
Himanshu Kaul345651.07
Sudhir Satpathy426919.69
Sanu Mathew5503.78
S. K. Hsu652152.06
amit agarwal7655.39
Ram Krishnamurthy865074.63
Shekhar Borkar94236494.95
Vivek De103024577.83