Name
Title | ||
|---|---|---|
A 12-bit, 5.5-μW single-slope ADC using intermittent working TDC with multi-phase clock signals |
Abstract | ||
|---|---|---|
We propose a single-slope ADC with an intermittent operational time-to-digital converter (TDC). Applying an n-bit TDC that uses a multi-phase-clock signal reduced the conversion time by a factor of 2", achieved timing consistency, and realized robust meta-stability. However, since a TDC needs to operate continuously, it required a large dissipation power. In this study, we focus on generating the PWM signal of a single-slope ADC and apply a scheme for limiting the TDC operation period in order to reduce TDC power dissipation. We designed and fabricated a 12-bit ADC, which consists of a 6-bit TDC and 6-bit-single-slope ADC, by using a 0.18-μm CMOS process. The ADC, at 100 kS/s, consumes 5.5 μW from a 1-V supply. Its INL and DNL were -1.9/+1.9 LSB and -0.8/+0.5 LSB, respectively. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ICECS.2014.7050099 | Electronics, Circuits and Systems |
Keywords | Field | DocType |
CMOS digital integrated circuits,PWM power convertors,clocks,time-digital conversion,CMOS process,DNL,INL,PWM signal,TDC operation period limition,TDC power dissipation reduction,analogue-digital conversion,conversion time reduction,intermittent operational time-digital converter,intermittent working TDC,multiphase clock signals,n-bit TDC,power 5.5 muW,robust metastability,single-slope ADC,size 0.18 mum,timing consistency,voltage 1 V,word length 12 bit,word length 6 bit | Computer science,Dissipation,Pulse-width modulation,Multi phase,12-bit,Cmos process,Electronic engineering,Limiting,Least significant bit | Conference |
Citations | PageRank | References |
0 | 0.34 | 3 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daisuke Uchida | 1 | 3 | 0.86 |
| M. Ikebe | 2 | 47 | 13.63 |
| Junichi Motohisa | 3 | 3 | 1.54 |
| Eiichi Sano | 4 | 7 | 6.98 |