Paper Info
Title
Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme
Abstract
A new packet data transfer scheme (PDTS) is introduced to reduce a configuration/control memory (CCM) size of a multiple-valued dynamic reconfigurable VLSI based on a logic-in-memory architecture. In the PDTS, the CCM size for memory access is proportional not to the number of distributed memory modules in the reconfigurable VLSI, but to the number of read operations in all the memories. Thus, remarkable reduction of the CCM size can be achieved in comparison with the conventional control scheme. Moreover, the PDTS contributes to fine-grain ON/OFF control of the current sources in Differential-Pair Circuits (DPCs) utilizing flag information which indicates whether the data is valid or invalid.
Year
DOI
Venue
2014
10.1109/ISMVL.2014.45
Multiple-Valued Logic
Keywords
Field
DocType
VLSI,integrated circuit design,integrated memory circuits,multivalued logic,multivalued logic circuits,CCM size,DPC,PDTS,bit-serial packet data transfer scheme,configuration-control memory size reduction,current source,differential-pair circuits,distributed memory modules,fine-grain ON-OFF control,flag information,logic-in-memory multiple-valued reconfigurable VLSI design,memory access,multiple-valued dynamic reconfigurable VLSI,read operation
Computer science,Network packet,Distributed memory,Electronic engineering,Control memory,Electronic circuit,Very-large-scale integration
Conference
ISSN
Citations 
PageRank 
0195-623X
2
0.49
References 
Authors
5
4
Name
Order
Citations
PageRank
Shintaro Harada120.49
Xu Bai2379.94
Michitaka Kameyama343199.93
Yoshichika Fujioka462.58