Name
Abstract | ||
|---|---|---|
Physical verification of an integrated circuit is a crucial step before manufacturing. In order to ensure the correctness of a design regarding the whole process flow, Design Rule Checking (DRC) is mandatory. As transistor size is reduced, the number of design rules to check increases exponentially. The increasing number of metal layers and heterogeneous integration possibilities are generating rules duplication, thus leading to a significant risk of mistakes, therefore being a relevant parameter to consider. This paper presents a new approach to write design rules using a high-level description language, offering noticeable modularity and reusability, available through a generic Design Rule Library (DRL) concept. This methodology fastens and simplifies DRC rules file writing by allowing substantial reduction of the number of lines to be hand written. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ICICDT.2014.6838599 | ICICDT |
Keywords | Field | DocType |
cmos integrated circuits,integrated circuit design,cmos technology,drc,drl concept,design rule checking,heterogeneous technology,high-level description language,high-level design rule library,integrated circuit,metal layers,physical verification,process flow,transistor size,cmos,design rule library,design rule manual,svrf,tcl/tvf,configurable,heterogeneous,photonics,shape,reliability | High-level design,Computer science,Correctness,Physical verification,Electronic engineering,CMOS,Design rule checking,Integrated circuit,Modularity,Reusability | Conference |
Citations | PageRank | References |
0 | 0.34 | 2 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gérald Cibrario | 1 | 28 | 5.30 |
| marjorie gary | 2 | 0 | 0.34 |
| fabien gays | 3 | 0 | 0.34 |
| k azizimourier | 4 | 0 | 0.34 |
| Olivier Billoint | 5 | 33 | 8.59 |
| Ogun Turkyilmaz | 6 | 40 | 4.41 |
| Olivier Rozeau | 7 | 12 | 2.91 |