Name
Playground
About
FAQ
GitHub
Playground
Shortest Path Finder
Community Detector
Connected Papers
Author Trending
Tidjani Négadi
Miquel Kegeleirs
Wagrowski, M.
Jhonathan Pinzon
Liangliang Shang
Evan Kidd
Giovanni Venturelli
Chen Ma
Jing-Sheng Wong
Radu Timofte
Home
/
Author
/
OLIVIER BILLOINT
Author Info
Open Visualization
Name
Affiliation
Papers
OLIVIER BILLOINT
CEA Grenoble, LETI, F-38054 Grenoble, France
20
Collaborators
Citations
PageRank
107
33
8.59
Referers
Referees
References
116
293
72
Search Limit
100
293
Publications (20 rows)
Collaborators (100 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Area and Cost Analysis of the Mixed Signal Circuits in a Novel Monolithic 3D Process
0
0.34
2021
Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology.
1
0.48
2019
Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges
0
0.34
2018
Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells.
0
0.34
2017
Cell-on-Buffer: New design approach for high-performance and low-power monolithic 3D integrated circuits.
0
0.34
2017
Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes
0
0.34
2016
Opportunities brought by sequential 3D CoolCube™ integration
0
0.34
2016
Recent advances in 3D VLSI integration
0
0.34
2016
UTBB FDSOI technology flexibility for ultra low power internet-of-things applications
1
0.39
2015
Intermediate BEOL process influence on power and performance for 3DVLSI
0
0.34
2015
From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges
1
0.37
2015
A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool.
15
1.03
2015
A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs
1
0.38
2015
An Unbalanced Area Ratio Study for High Performance Monolithic 3D Integrated Circuits
3
0.59
2015
3D technologies for reconfigurable architectures
0
0.34
2014
27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding F MAX tracking
0
0.34
2014
3DCoB: A new design approach for Monolithic 3D Integrated circuits.
3
0.58
2014
A high-level design rule library addressing CMOS and heterogeneous technologies
0
0.34
2014
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs
6
0.60
2013
Fpga Prototyping Of Large Reconfigurable Adpll Network For Distributed Clock Generation
2
0.45
2013
1
