Paper Info
Title
25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation
Abstract
The recent revolution in handheld computing with high-speed cellular network made mobile processors have multi-cores and powerful 3D graphic engines that support FHD (1920×1080) or even higher resolutions. Consequently, the memory bandwidth requirement has also been increasing, requiring a next-generation mobile DRAM standard. In this paper, we present a power-efficient LPDDR4 SDRAM operating at 3.2Gb/s/pin. Our LPDDR4 DRAM offers 2× bandwidth with improved power efficiency over LPDDR3 SDRAM's, due to the 2-channel architecture and low-voltage-swing terminated logic (LVSTL) [1]. Moreover, the supply voltage is further reduced to 1.0V in this work, 0.1V lower than the LPDDR4 standard, for extra power saving.
Year
DOI
Venue
2014
10.1109/ISSCC.2014.6757500
Solid-State Circuits Conference Digest of Technical Papers
Keywords
DocType
ISSN
dram chips,sram chips,error correction codes,logic circuits,2-channel architecture,3d graphic engines,dram core operation,lvstl,handheld computing,high-speed cellular network,integrated ecc engine,integrated error-correction coding,low-voltage-swing terminated logic,memory bandwidth requirement,mobile multicore processors,next-generation mobile dram standard,power-efficient lpddr4 sdram,storage capacity 8 gbit,voltage 1.0 v
Conference
0193-6530
Citations 
PageRank 
References 
13
1.36
1
Authors
24
Name
Order
Citations
PageRank
Tae-young Oh1568.23
Hoeju Chung238428.25
Youngchul Cho38713.10
jangwoo ryu4131.36
Ki-Won Lee5232.80
changyoung lee6131.36
Hyoung-Joo Kim71108374.05
min soo jang8131.36
gongheum han9131.36
kihan kim10132.38
daesik moon11163.87
Seung-Jun Bae1216732.40
joonyoung park13141.77
Kyung-Soo Ha14527.63
Su-Yeon Doo15314.82
jungbum shin16132.04
Chang-Ho Shin17456.84
kiseok oh18131.36
doohee hwang19131.36
taeseong jang20131.36
chulsung park21131.36
Kwang-Il Park2216325.68
Jung-Bae Lee2317917.70
Joo Sun Choi2423924.11