Paper Info
Title
Timing characterization of clock buffers for clock tree synthesis
Abstract
It is formidable to embed iterative simulations into the clock tree synthesis process to verify the skew and slew constraints. Instead, accurate and simple timing models for clock buffers are traditionally used so as to perform clock tree synthesis with sufficient accuracy. Two-pole RC and/or piecewise linear models accurately models the gate delay without a waveform dependency for a wide range of waveform properties. However, they unnecessarily complicate the problem for the time modeling of clock buffers where, unlike logic gates, the input and output waveform properties are similar. Look-up table-based approaches are traditionally used in order to obtain the clock buffer timing with inputs being the input slew and the output capacitance. However, the effective capacitance estimation of the highly resistive wires of sub-45nm technologies is a challenge, making it hard to identify the output capacitance. Also, the multiple or dynamically-scaled voltage levels of the current designs necessitate a costly LUT-based pre-characterization process. In this work, a timing estimation scheme for clock buffers is proposed which models both the delay and the slew as linear equations, bypassing the costly LUT characterization process. The experimental results performed with SAED 32nm buffer library show that the proposed timing model can achieve a maximum absolute value error of ≈5ps to ≈10ps for the buffer timing compared to SPICE simulations. Furthermore, the proposed timing model provides an error from 0.2% to 4.6% at different timing constraints and operating voltage levels, when used for insertion delay computation.
Year
DOI
Venue
2014
10.1109/ICCD.2014.6974686
Computer Design
Keywords
Field
DocType
RC circuits,SPICE,buffer circuits,clocks,iterative methods,network synthesis,poles and zeros,SPICE,clock buffer timing,clock buffers,clock tree synthesis,insertion delay computation,iterative simulations,linear equations,logic gates,look-up table,piecewise linear models,size 45 nm,timing characterization
Clock gating,Timing failure,Computer science,Control theory,Clock domain crossing,Real-time computing,Electronic engineering,Static timing analysis,Clock skew,Synchronous circuit,Digital clock manager,CPU multiplier
Conference
ISSN
Citations 
PageRank 
1063-6404
4
0.46
References 
Authors
11
3
Name
Order
Citations
PageRank
Sitik, C.140.46
Scott Lerner273.56
Baris Taskin322740.82