Title
At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs
Abstract
In this work, we propose a distributed functional test mechanism for NoCs which scales to large-scale networks with general topologies and routing algorithms. Each router and its links are tested using neighbors in different phases. The router under test is in test mode while all other parts of the NoC are operational. We use triple module redundancy (TMR) for the robustness of all testing components that are added into the switch. Experimental results show that our functional test approach can detect stuck-at, short and delay faults in the routers and links. Our approach achieves 100 percent stuck-at fault coverage for the data path and 85 percent for the control paths including routing logic, FIFO's control path, and the arbiter of a $(5 \times 5)$ router. We also show that our approach is able to detect delay faults in critical control and data paths. Synthesis results show that the area overhead of our test components with TMR support is 20 percent for covering stuck-at, delay, and short-wire faults and 7 percent for covering only stuck-at and delay faults in the $(5 \times 5)$ router. Simulation results show that our online testing approach has an average latency overhead of 3 percent in PARSEC traffic benchmarks on an $(8 \times 8)$ NoC.
Year
DOI
Venue
2014
10.1109/TC.2013.202
Computers, IEEE Transactions  
Keywords
Field
DocType
circuit switching,fault diagnosis,integrated circuit testing,network routing,network-on-chip,FIFO,NoCs,PARSEC traffic benchmarks,TMR,arbiter,at-speed distributed functional testing,control path,critical control,data paths,delay fault detection,distributed functional test mechanism,functional test approach,general topologies,large-scale networks,links,logic fault detection,router,routing algorithms,routing logic,short fault detection,stuck-at fault coverage,stuck-at fault detection,switch,triple module redundancy,NoC testing,delay fault,functional test,online testing
Logic gate,Arbiter,Fault coverage,FIFO (computing and electronics),Computer science,Parallel computing,Robustness (computer science),Network topology,Real-time computing,Redundancy (engineering),Router
Journal
Volume
Issue
ISSN
63
3
0018-9340
Citations 
PageRank 
References 
24
0.78
39
Authors
3
Name
Order
Citations
PageRank
Mohammad Reza Kakoee1723.99
Valeria Bertacco2136586.93
Luca Benini3131161188.49