Name
Title | ||
|---|---|---|
The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap |
Abstract | ||
|---|---|---|
The system driver models for microprocessor (MPU) and system-on-chip (SOC) in the International Technology Roadmap for Semiconductors [21] (ITRS) determine the roadmap of underlying technology requirements across devices, patterning, interconnect, test, design and other semiconductor supplier industries. In this paper, we describe several fundamental changes in the ITRS MPU and SOC system driver models as of the recently-released 2013 edition of the roadmap. We first present new A-factor (i.e., layout density) models for the logic and memory components of the MPU and SOC drivers; these updated density models comprehend the industry's shift to FinFET devices below the foundry 20nm node. We also describe updated architectural, total chip area, and total chip power models for the MPU and SOC drivers. Notably, we model the growing uncore portion of MPU products, and the growing presence of graphic processing units (GPUs) and other peripheral cores (PEs) in SOC architectures. The updated SOC architectural model enables more realistic scenario-based power modeling for the SOC driver. The 2013 ITRS update of system driver models embodies extensive calibration with foundry data as well as product structural analysis reports from a leading analysis firm (Chipworks). The model calibration reveals that the industry has contended with a “scaling gap” since 2008, whereby traditional Moore's-Law density scaling of 2× per node has failed due to patterning limitations on layout design, as well as manufacturability and performability challenges of Metal-1 half-pitch (M1HP) scaling. Growing design margins due to reliability, yield, variability, etc. have also contributed to the slowdown of density scaling. We describe how this scaling gap can potentially be compensated if the semiconductor industry urgently pursues design-based equivalent scaling (DES), which substantially changes the area and power model trajectories of MPUs and SOCs in the ITRS System Dri- ers Chapter. Finally, we note that as a consequence of the updated A-factor, area and power models in the 2013 ITRS, the industry now faces a 20% more daunting power management challenge than had been predicted in the 2011 roadmap. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ICCD.2014.6974675 | Computer Design |
Keywords | Field | DocType |
MOSFET circuits,driver circuits,graphics processing units,integrated circuit design,integrated circuit modelling,microprocessor chips,system-on-chip,DES,FinFET devices,GPU,ITRS MPU,International Technology Roadmap for Semiconductors,M1HP scaling,MPU products,Moore's law densit,PE,SOC architectural model,SOC system driver models,chip area,chip power models,density models,design-based equivalent scaling,foundry data,graphic processing units,layout density,metal-1 half-pitch scaling,microprocessor,peripheral cores,power management,power modeling,product structural analysis,semiconductor supplier industries,system-on-chip | Power management,Page layout,Computer science,Microprocessor,Uncore,Chip,International Technology Roadmap for Semiconductors,Real-time computing,Design for manufacturability,Architectural model,Embedded system | Conference |
ISSN | Citations | PageRank |
1063-6404 | 5 | 0.53 |
References | Authors | |
2 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wei-Ting Jonas Chan | 1 | 69 | 6.70 |
| Andrew B. Kahng | 2 | 7582 | 859.06 |
| Siddhartha Nath | 3 | 240 | 15.01 |
| Ichiro Yamamoto | 4 | 5 | 0.53 |