Paper Info
Title
Fast STA prediction-based gate-level timing simulation
Abstract
Traditional dynamic simulation with standard delay format (SDF) back-annotation cannot be reliably performed on large designs. The large size of SDF files makes the event-driven timing simulation extremely slow as it has to process an excessive number of events. In order to accelerate gate-level timing simulation we propose an automated fast prediction-based gate-level timing simulation that combines static timing analysis (STA) at the block level with dynamic timing simulation at the I/O interfaces. We demonstrate that the proposed timing simulation can be done earlier in the design cycle in parallel with synthesis.
Year
DOI
Venue
2014
10.7873/DATE.2014.261
Design, Automation and Test in Europe Conference and Exhibition
Keywords
Field
DocType
application specific integrated circuits,circuit simulation,field programmable gate arrays,integrated circuit design,system-on-chip,ASIC-FPGA design flow,automated fast prediction-based gatelevel timing simulation,dynamic timing simulation,standard delay format,static timing analysis,system-on-chip designs,ASIC,Gate-level timing,Opencores,RTL,Verilog,dynamic timing simulation,static timing analysis
System on a chip,Computer science,Field-programmable gate array,Application-specific integrated circuit,Real-time computing,Integrated circuit design,Static timing analysis,Verilog,Standard Delay Format,Dynamic simulation
Conference
ISSN
Citations 
PageRank 
1530-1591
2
0.49
References 
Authors
5
2
Name
Order
Citations
PageRank
Tariq B. Ahmad120.49
Maciej J. Ciesielski262974.80