Name
Abstract | ||
|---|---|---|
Simulation of the RTL model is one of the first and mandatory steps of the design verification flow. Such a simulation needs to be repeated often due to the changing nature of the design in its early development stages and after consecutive bug fixing. Despite its relatively high level of abstraction, RTL simulation is a very time consuming process, often requiring nightly or week-long regression runs. In this work, we propose an original approach to accelerating RTL simulation that leverages parallelism offered by multi-core machines. However, in contrast to traditional, parallel distributed RTL simulation, the proposed method accelerates RTL simulation in temporal domain by dividing the entire simulation run into independent simulation slices, each to be run on a separate core. It is combined with fast simulation model at ESL level that provides the required initial state for each independent simulation slice. The paper describes the basic idea of the method and provides some initial experimental results showing its effectiveness in improving RTL simulation performance in an automated way. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/DDECS.2014.6868766 | Warsaw |
Keywords | Field | DocType |
digital simulation,formal verification,multiprocessing systems,parallel processing,abstraction level,design verification flow,fast simulation model,fast time-parallel C-based event-driven RTL simulation,multicore machines,parallel distributed RTL simulation,register transfer level,C,ESL,RTL,Simulation,SystemC,Testbench,Verfication,Verilog | Logic gate,Division (mathematics),Load modeling,Computer science,Parallel computing,Real-time computing,SystemC,Verilog,Multi-core processor | Conference |
ISSN | Citations | PageRank |
2334-3133 | 0 | 0.34 |
References | Authors | |
4 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tariq Bashir Ahmad | 1 | 0 | 0.34 |
| Maciej J. Ciesielski | 2 | 629 | 74.80 |