Name
Abstract | ||
|---|---|---|
In this paper, a novel method to synthesize circuits based on threshold logic gates (TLG) is proposed. Synthesis considering TLGs is quite relevant, since threshold logic has been revisited as a promising alternative to conventional CMOS integrated circuits due to its suitability to emerging technologies, such as tunneling diodes, memristors and spintronics devices. A constructive process is applied to generate optimized TLG networks taking into account multiple goals and design costs, including gate count, logic depth and number of interconnections. Experiments carried out over MCNC benchmark circuits have shown an average gate count reduction of circa 32%, reaching up to 54% in some cases, in comparison to related approaches. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ISCAS.2014.6865146 | Circuits and Systems |
Keywords | Field | DocType |
CMOS logic circuits,logic design,threshold logic,CMOS integrated circuits,MCNC benchmark circuits,average gate count reduction,constructive approach,design costs,gate count,logic depth,memristors,optimized TLG networks,spintronics devices,threshold logic circuit synthesis,tunneling diodes,Digital circuit,TLG,functional composition,logic synthesis,threshold logic,threshold networks | Logic synthesis,Logic gate,High Threshold Logic,Pass transistor logic,Computer science,AND-OR-Invert,Logic optimization,Electronic engineering,Resistor–transistor logic,Logic family | Conference |
ISSN | Citations | PageRank |
0271-4302 | 0 | 0.34 |
References | Authors | |
6 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Augusto Neutzling | 1 | 20 | 2.93 |
| Mayler G. A. Martins | 2 | 88 | 10.08 |
| Renato P. Ribas | 3 | 204 | 33.52 |
| André Inácio Reis | 4 | 0 | 0.34 |