Paper Info
Title
Employing a Timed Colored Petri Net to accomplish an accurate model for Network-on-Chip performance evaluation
Abstract
Network-on-Chip (NoC) is the most promising communication architecture for modern System-on-Chip (SoC). A system level analysis with a sound NoC model may provide an efficient NoC implementation. In this paper, we propose an accurate NoC model for performance evaluation based on Timed and Colored Petri Net (TCPN). The TCPN provides a detailed modeling of discrete event systems, enabling further evaluation of logical and temporal aspects with great precision. Experimental results with a 5×5 mesh NoC under synthetic and real traffic situations demonstrate the TCPN model efficiency in the latency predictability with low errors when compared with VHDL/SystemC simulation. Additionally, this work shows the ability of the model to allow fast building of different models and changes upon NoC architectural features such as routing algorithm and buffer length.
Year
DOI
Venue
2014
10.1109/ISQED.2014.6783306
Quality Electronic Design
Keywords
Field
DocType
Petri nets,integrated circuit modelling,network-on-chip,NoC architectural features,NoC implementation efficiency,SoC,TCPN model efficiency,VHDL-SystemC simulation,buffer length,discrete event system modeling,latency predictability,logical aspect,mesh NoC,network-on-chip performance evaluation,real traffic situation,routing algorithm,sound NoC model,synthetic traffic situation,system level analysis,system-on-chip,temporal aspect,timed colored Petri net,NoC,Petri Net Modeling,latency evaluation
Logical conjunction,Predictability,Petri net,Latency (engineering),Computer science,Network on a chip,Colored petri,Real-time computing,SystemC,VHDL,Embedded system
Conference
ISSN
Citations 
PageRank 
1948-3287
0
0.34
References 
Authors
0
4
Name
Order
Citations
PageRank
Jarbas Silveira1206.62
Paulo César Cortez200.34
Giovanni Cordeiro Barroso3116.31
Cesar A. M. Marcon412028.83