Jarbas Silveira - Citegraph

Author Info

Name	Affiliation	Papers
JARBAS SILVEIRA	DETI-UFC Federal University of Ceará Fortaleza, Brazil	18
Collaborators	Citations	PageRank
49	20	6.62
Referers	Referees	References
65	310	139

Search Limit

100310

Publications (18 rows)

Collaborators (49 rows)

Referers (65 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Optimizing RISC-V ISA Usage by Sharing Coprocessors on MPSoC	0	0.34	2020
Optimized buffer protection for network-on-chip based on Error Correction Code	0	0.34	2020
PCoSA: A product error correction code for use in memory devices targeting space applications.	0	0.34	2020
CLC-A: An Adaptive Implementation of the Column Line Code (CLC) ECC	0	0.34	2020
Performance Analysis of Depth Intra-Coding in 3D-HEVC.	2	0.37	2019
PHICC: an error correction code for memory devices	0	0.34	2019
Optimized Fault-Tolerant Buffer Design for Network-on-Chip Applications	0	0.34	2019
An Extensible Code for Correcting Multiple Cell Upset in Memory Arrays	0	0.34	2018
Evaluation of multiple bit upset tolerant codes for NoCs buffering	2	0.40	2017
Latency reduction of fault-tolerant NoCs by employing multiple paths.	0	0.34	2017
An efficient, low-cost ECC approach for critical-application memories.	1	0.36	2017
Scenario preprocessing approach for the reconfiguration of fault-tolerant NoC-based MPSoCs.	2	0.39	2016
A security aware routing approach for NoC-based MPSoCs.	7	0.56	2016
A correction code for multiple cells upsets in memory devices for space applications	1	0.40	2016
Smart Reconfiguration Approach for Fault-Tolerant NoC Based MPSoCs	1	0.35	2015
Preprocessing of Scenarios for Fast and Efficient Routing Reconfiguration in Fault-Tolerant NoCs	1	0.35	2015
A fault prediction module for a fault tolerant NoC operation	3	0.39	2015
Employing a Timed Colored Petri Net to accomplish an accurate model for Network-on-Chip performance evaluation	0	0.34	2014

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