Name
Abstract | ||
|---|---|---|
Dynamic power consumption is directly related tothe number of the signal transitions in a circuit. Glitches are undesired spurious transitions caused by inputs of a gate arriving at different times, instead of arriving together, thus causing unnecessary power dissipation. Our objective in this paper is to reduce the number of glitches in a circuit to reduce dynamic power. We do so by clock skew scheduling, where different flipflopsreceive clocks at different times. We formulate thescheduling as an Integer linear Programming problem andderive vector-independent clock skew schedule to reduce glitches. We also propose linear objective functions based on timing window of gates for optimization. The proposed method was evaluated on ISCAS-89 benchmark circuits using dynamic simulation. Results show that we achieve an average reduction of ~32% in glitch power. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ISVLSI.2014.75 | ISVLSI |
Keywords | Field | DocType |
clocks,flip-flops,integer programming,linear programming,scheduling,ISCAS-89 benchmark circuits,clock skew scheduling,dynamic power,flip-flops,glitch power reduction,integer linear programming,signal transitions,spurious transitions,Clock skew scheduling,Dynamic power,Glitches,Integer Linear programming | Glitch,Logic gate,Computer science,Electronic engineering,Integer programming,Dynamic demand,Clock skew,Linear programming,Electronic circuit,Dynamic simulation | Conference |
ISSN | Citations | PageRank |
2159-3469 | 2 | 0.42 |
References | Authors | |
10 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Arunkumar Vijayakumar | 1 | 44 | 4.65 |
| Sandip Kundu | 2 | 1103 | 137.18 |