Name
Abstract | ||
|---|---|---|
This paper presents a combined solution to the Through-Silicon-Via (TSV) placement and mapping of cores to routers in a three-dimensional Network-on-Chip (NoC) design. It takes care of TSV geometries and communication requirements between cores. Comparison has been carried out with the recent 3D mapping results. Both static and dynamic performance have been considered. It shows that an intelligent placement of TSVs coupled with mapping can improve the performance significantly. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/VLSI-SoC.2014.7004177 | Very Large Scale Integration |
Keywords | DocType | Citations |
integrated circuit design,network-on-chip,three-dimensional integrated circuits,3D mapping,3D mesh based network-on-chip,NoC design,TSV geometry,three-dimensional network-on-chip design,through silicon via mapping strategy,through silicon via placement strategy | Conference | 3 |
PageRank | References | Authors |
0.37 | 14 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kanchan Manna | 1 | 44 | 5.53 |
| Santanu Chattopadhyay | 2 | 343 | 44.89 |
| Indranil Sengupta | 3 | 498 | 55.11 |