Kanchan Manna - Citegraph

Author Info

Name	Affiliation	Papers
KANCHAN MANNA	Indian Inst Technol, Sch Informat Technol, Kharagpur 721302, W Bengal, India	14
Collaborators	Citations	PageRank
20	44	5.53
Referers	Referees	References
104	364	241

Search Limit

100364

Publications (14 rows)

Collaborators (20 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Thermal-Aware Partitioning and Encoding of Power-Gated FSM.	0	0.34	2019
Thermal-aware Test Scheduling Strategy for Network-on-Chip based Systems.	0	0.34	2019
Thermal-Aware Application Mapping Strategy for Network-on-Chip Based System Design.	2	0.37	2018
Integrated Through-Silicon Via Placement and Application Mapping for 3D Mesh-Based NoC Design.	3	0.43	2016
Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs.	1	0.35	2016
Thermal-Aware Design and Test Techniques for Two-and Three-Dimensional Networks-on-Chip.	0	0.34	2016
A Constructive Heuristic for Application Mapping onto Mesh Based Network-on-Chip.	5	0.42	2015
Thermal-aware multifrequency network-on-chip testing using particle swarm optimisation	3	0.37	2015
TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning	1	0.35	2015
Through silicon via placement and mapping strategy for 3D mesh based Network-on-Chip	3	0.37	2014
A spare router based reliable Network-on-Chip design	7	0.47	2014
Extending Kernighan-Lin partitioning heuristic for application mapping onto Network-on-Chip.	10	0.53	2014
Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization.	2	0.36	2013
A Comparative Performance Evaluation of Network-on-Chip Architectures under Self-Similar Traffic	7	0.49	2009

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