Paper Info
Title
A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECC
Abstract
A 0.4 V single cycle 75 kbit SRAM macro protected with a multi-bit upset (MBU) correcting circuit is fabricated in a 28 nm LP-CMOS process. The novel error correcting circuit (ECC) is capable of 3-bit adjacent error correction and 8bit adjacent error detection. Simulation results show that the code provides a 2.35x improvement in corrected soft error rate (SER) over a Bose-Chaudhuri-Hocquenghem (BCH) double error correcting (DEC) code at a raw-SER of 1300 FIT/Mb while requiring 3 fewer check-bits. Further an alternative 2-bit adjacent error correcting implementation provides an corrected-SER approximately equal to the BCH DEC code for the same check-bit overhead as a single error correcting double error detecting (SEC-DED) code in the same error channel. Measurement results confirm an average active energy of 0.015 fJ/bit and leakage current of 10.1 pA/bit.
Year
DOI
Venue
2014
10.1109/CICC.2014.6946091
Custom Integrated Circuits Conference
Keywords
Field
DocType
BCH codes,CMOS integrated circuits,SRAM chips,error correction codes,error detection codes,radiation hardening (electronics),3-adjacent MBU correcting ECC,BCH DEC codes,Bose-Chaudhuri-Hocquenghem double error correcting code,LP-CMOS process,SEC-DED code,SER,SRAM macro,adjacent error correction,adjacent error detection,check bit overhead,corrected soft error rate,error channel,error correcting circuit,leakage current,multibit upset correcting circuit,single error correcting double error detecting codes,size 28 nm,storage capacity 75 Kbit,voltage 0.4 V,word length 2 bit,word length 3 bit,word length 8 bit
Coding gain,Error floor,Soft error,Computer science,Low-density parity-check code,Electronic engineering,Static random-access memory,CMOS,Macro
Conference
Citations 
PageRank 
References 
0
0.34
3
Authors
2
Name
Order
Citations
PageRank
Adam Neale1102.00
Manoj Sachdev266988.45