Paper Info
Title
Multi-channel testing architecture for high-speed eye-diagram using pin electronics and subsampling monobit reconstruction algorithms
Abstract
This paper proposes a new multi-channel testing architecture for high-speed eye-diagram. The proposed architecture reconstructs the eye-diagram of a multi-Gbps bit pattern with the combination of pin electronics and reconstruction algorithms. A scalability of the test system significantly increases in behalf of a monobit receiver and its designated reconstruction algorithm. A novel reconstruction algorithm using monobit receiver and subsampling clock enables the test system to monitor the signal quality in low-cost. The proposed architecture is implemented and demonstrated in a hardware prototype. Experiment with the hardware prototype shows that an eye-diagram of 3.2Gbps bit pattern can be reconstructed within sub-picosecond resolution by the proposed method with subsampling clock (below 100MHz).
Year
DOI
Venue
2014
10.1109/VTS.2014.6818768
VLSI Test Symposium
Keywords
Field
DocType
automatic test equipment,clocks,electronics packaging,field programmable gate arrays,integrated circuit measurement,integrated circuit testing,bit rate 3.2 Gbit/s,hardware prototype,high-speed eye-diagram,monobit receiver,multiGbps bit pattern,multichannel testing architecture,pin electronics,signal quality,subpicosecond resolution,subsampling clock,subsampling monobit reconstruction algorithms,test system,Eye-diagram,High-speed Bit pattern,Monobit receiver,Pin Electronic
Synchronization,Architecture,Computer science,Field-programmable gate array,Algorithm,Diagram,Real-time computing,Electronic engineering,Multi channel,Reconstruction algorithm,Electronics,Scalability
Conference
ISSN
Citations 
PageRank 
1093-0167
1
0.38
References 
Authors
7
4
Name
Order
Citations
PageRank
Thomas Moon1153.75
Hyun Woo Choi2356.71
David C. Keezer36817.00
Abhijit Chatterjee41949269.99