Paper Info
Title
A 5 Gb/s, 10 ns Power-On-Time, 36 W Off-State Power, Fast Power-On Transmitter for Energy Proportional Links
Abstract
A fast power-on transmitter architecture that enables energy proportional communication for server and mobile platforms is presented. The proposed architecture and circuit techniques achieve fast power-on capability in voltage mode output driver by using fast-digital regulator, and in the clock multiplier by accurate frequency pre-setting and periodic reference insertion. To ease timing requirements, an improved edge replacement logic circuit for the clock multiplier is proposed. The proposed transmitter demonstrates energy proportional operation over wide variations of link utilization, and is therefore suitable for energy efficient links. Fabricated in 90 nm CMOS technology, the voltage mode driver and the clock multiplier achieve power-on-time of only 2 ns and 10 ns, respectively. By using highly scalable digital architecture with accurate frequency pre-setting and instantaneous phase acquisition, the prototype MDLL-based clock multiplier achieves 10 ns (3 reference cycles) power-on-time, 2 psrms long-term absolute jitter at 2.5 GHz output frequency. The proposed fast power-on transmitter architecture consumes 4.8 mW/36 W on/off-state power from 1.1 V supply, has 10 ns total power-on time, and achieves 100 effective data rate scaling (5 Gb/s-0.048 Gb/s), while scaling the power and energy efficiency by only 50 (4.8 mW-0.095 mW) and 2 (1-2 pJ/Bit), respectively. The proposed transmitter occupies an active die area of 0.3 mm .
Year
DOI
Venue
2014
10.1109/JSSC.2014.2345764
Solid-State Circuits, IEEE Journal of  
Keywords
DocType
Volume
CMOS integrated circuits,driver circuits,multiplying circuits,telecommunication power management,transmitters,bit rate 5 Gbit/s to 0.048 Gbit/s,circuit techniques,data rate scaling,edge replacement logic circuit,energy efficiency,energy efficient links,energy proportional communication,energy proportional links,fast power-on transmitter architecture,fast-digital regulator,frequency 2.5 GHz,frequency pre-setting,instantaneous phase acquisition,link utilization,long-term absolute jitter,mobile platforms,periodic reference insertion,power 36 W,power 36 muW,power 4.8 mW to 0.095 mW,power efficiency,prototype MDLL-based clock multiplier,scalable digital architecture,server,size 90 nm,time 10 ns,time 2 ns,voltage 1.1 V,voltage mode output driver,Burst mode,I/O,digital regulator,energy efficient,energy proportional,fast power-on,multiplying delay locked loop (MDLL),serial link,transmitter
Journal
49
Issue
ISSN
Citations 
10
0018-9200
0
PageRank 
References 
Authors
0.34
0
4
Name
Order
Citations
PageRank
Tejasvi Anand111016.98
Amr Elshazly224228.08
Talegaonkar, M.300.34
Young, B.400.34