Name
Title | ||
|---|---|---|
A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS |
Abstract | ||
|---|---|---|
A single-cycle tree-based 64-bit binary comparator with constant-delay (CD) logic realized in a 65-nm, 1-V CMOS process is presented in this paper. Unlike dynamic logic yet domino-compatible, CD logic predischarges the output to logic “0” and conditionally makes a transition to logic “1” through the critical-path CLK PMOS transistors for an NMOS transistor network. The constant delay (regardless of the fan-in) feature makes it up to 2× faster than a dynamic logic gate during the D-Q mode for a complex logic such as a two-bit binary comparator. The proposed comparator's architecture is divided into two stages, where the first stage adapts a novel tree comparator structure specifically designed for static logic to achieve low-power consumption and the second stage utilizes CD logic to realize high performance without sacrificing the overall energy efficiency. At 1-V supply, the proposed comparator's measured delay is 167 ps, and has an average power and a leakage power of 2.34 mW and 0.06 mW, respectively. At 0.3-pJ iso-energy or 250-ps iso-delay budget, the proposed comparator with CD logic is 20% faster or 17% more energy-efficient compared to a comparator implemented with just the static logic. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TCSI.2013.2268591 | Circuits and Systems I: Regular Papers, IEEE Transactions |
Keywords | Field | DocType |
CMOS logic circuits,MOSFET,comparators (circuits),CD logic,CMOS process,D-Q mode,NMOS transistor network,complex logic,constant delay feature,constant-delay logic,critical-path CLK PMOS transistors,dynamic logic gate,energy 0.3 pJ,energy efficiency,iso-delay budget,low-power consumption,power 0.6 mW,power 2.34 mW,single-cycle binary tree comparator,size 65 nm,static logic,time 167 ps,time 250 ps,tree comparator structure,two-bit binary comparator,voltage 1 V,Binary comparator,constant-delay logic,digital arithmetic | Diode–transistor logic,Logic gate,Pass transistor logic,Computer science,AND-OR-Invert,Electronic engineering,Comparator applications,Logic level,Dynamic logic (digital electronics),Logic family | Journal |
Volume | Issue | ISSN |
61 | 1 | 1549-8328 |
Citations | PageRank | References |
2 | 0.40 | 7 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pierce I.-Jen Chuang | 1 | 2 | 0.40 |
| Manoj Sachdev | 2 | 669 | 88.45 |
| Vincent C. Gaudet | 3 | 66 | 5.62 |