Name
Title | ||
|---|---|---|
An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique |
Abstract | ||
|---|---|---|
An extremely low power and area efficient threshold configuring ADC (TC-ADC) for time interleaved ADC is proposed. The threshold configuring comparator (TCC) performs a binary search. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm2 and when calibration circuit included, 0.0058 mm2. With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ASPDAC.2014.6742859 | Design Automation Conference |
Keywords | Field | DocType |
CMOS integrated circuits,analogue-digital conversion,comparators (circuits),interpolation,low-power electronics,CMOS techonology,SAR ADC,TCC,calibration circuit,extremely area efficient threshold,size 40 nm,source voltage shifting technique,successive approximation register,threshold configuring comparator,threshold interpolation,time interleaved ADC,voltage 0.5 V,voltage 0.7 V | Comparator,Computer science,Voltage source,Interpolation,Voltage,CMOS,Effective number of bits,Electronic engineering,Successive approximation ADC,Electrical engineering,Low-power electronics | Conference |
ISSN | Citations | PageRank |
2153-6961 | 1 | 0.36 |
References | Authors | |
3 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kentaro Yoshioka | 1 | 54 | 9.04 |
| Shikata, A. | 2 | 5 | 0.90 |
| Sekimoto, R. | 3 | 5 | 0.90 |
| Kuroda, T. | 4 | 20 | 3.09 |