Name
Title | ||
|---|---|---|
Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures |
Abstract | ||
|---|---|---|
This paper presents novel ultra-low power processor based on “Normally-off (N-off)” architecture, on which processors can remain in “off state” even during a short standby state. To realize “N-off” for high-performance (HP-) processors, we have developed novel STT-MRAM circuits and nonvolatile cache memories using them. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ISICIR.2014.7029504 | ISIC |
Keywords | Field | DocType |
mram devices,cache storage,low-power electronics,hp-processor,n-off architecture,stt-mram-based last level cache,high performance ultralow power processor,nonvolatile cache memory,normally-off architecture,spin torque transfer magnetic random access memory,nonvolatile memory,cache memory,central processing unit | Pipeline burst cache,Computer architecture,Uniform memory access,Cache pollution,Cache,Computer science,Distributed memory,Cache-only memory architecture,Cache algorithms,Smart Cache | Conference |
ISSN | Citations | PageRank |
2325-0631 | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shinobu Fujita | 1 | 180 | 22.11 |
| Hiroki Noguchi | 2 | 145 | 20.04 |
| Kazutaka Ikegami | 3 | 43 | 6.79 |
| susumu takeda | 4 | 0 | 1.01 |
| kumiko nomura | 5 | 0 | 0.34 |
| Abe, K. | 6 | 46 | 6.27 |