Novel memory hierarchy with e-STT-MRAM for near-future applications | 0 | 0.34 | 2017 |
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme | 6 | 0.46 | 2016 |
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture | 16 | 1.10 | 2015 |
Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures | 0 | 0.34 | 2014 |
Pictogram-based tablet application enabling patient input of emotions and behaviors. | 0 | 0.34 | 2014 |
Development of robot hand with multi-directional variable stiffness for human-care services | 0 | 0.34 | 2012 |
Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies | 3 | 0.42 | 2010 |
3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture | 10 | 1.12 | 2007 |
Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices. | 1 | 0.65 | 2006 |
Extension of SMIL with QoS control and its implementation | 2 | 0.40 | 2000 |
Verification of an advanced space teleoperation system using Internet | 8 | 0.77 | 2000 |